Isolating Micro-Machined Accelerometer Zero-G Bias Shifts under Static Thermal Cycles
Static thermal zero-g bias shifts in MEMS accelerometers are isolated by enforcing prolonged thermal dwell periods to decouple stress creep from thermal gradients.
Switched-Capacitor ASIC
Circuit Architecture
Integrated circuits designed for sensor interfaces often use charge-transfer techniques to implement precise analog signal processing without the need for large on-chip resistors. This type of device, known as a switched-capacitor ASIC, utilizes a network of switches and capacitors controlled by non-overlapping clock phases to emulate resistive behavior and perform filtering, gain, or analog-to-digital conversion. This approach takes advantage of the high precision with which capacitor ratios can be matched in modern semiconductor manufacturing.
Operation Principle
The fundamental mechanism involves transferring charge between capacitors by opening and closing electronic switches in a specific sequence. During the first clock phase, a capacitor is connected to the input signal and charges to the input voltage. In the second phase, the capacitor is reconnected to the input of an amplifier, transferring its stored charge to a feedback capacitor.
This charge-transfer process is repeated at a high frequency, creating an effective resistance that depends solely on the switching frequency and the capacitance value.
Metrological Precision
Clock jitter and switch non-idealities represent the primary sources of error that can limit the measurement accuracy of these devices. Charge injection occurs when the electronic switches turn off, releasing a small amount of charge into the signal path and causing a voltage offset. This offset must be compensated for using differential circuit designs or correlated double sampling techniques.
These compensation methods ensure that the circuit maintains high linearity and low noise over a wide temperature range.
Integration Constraint
Laying out the capacitors on the semiconductor die requires careful matching strategies to minimize the effects of manufacturing gradients. A common-centroid layout is typically used to ensure that the capacitors are exposed to the same thermal and process variations.