Charge Injection
Metal-oxide-semiconductor sampled-data devices translate continuous analog voltages into discrete digital representations through timed charge packets routed across microscopic semiconductor switches. Switched-capacitor ADCs rely on precision metal-insulator-metal structures alongside metal-oxide-semiconductor field-effect transistors to route, scale, and compare electrical charge rather than continuous current. Each sampling phase opens and closes MOS switches, depositing residual charge onto sensitive summing nodes which produces an inherent error voltage known as clock feedthrough.
Non-ideal gate capacitance coupling creates an offset proportional to clock signal slew rates and overlapping control phases. Eliminating this parasitic addition requires differential circuit topologies where complementary switching cancels common-mode charge injection errors at the comparator input.
Quantization Noise
Resolution limits arise directly from finite voltage step sizes defined by the reference voltage divided by two raised to the power of the bit depth. Switched-capacitor ADCs distribute conversion errors evenly across the Nyquist bandwidth during successive approximation or cyclic conversion sequences. Thermal noise originating from switch channel resistance combines with sampled charge uncertainty to establish the absolute noise floor of the integrated circuit.
Oversampling techniques push the resulting noise spectrum beyond the region of interest, allowing digital low-pass filtering to improve the effective signal-to-noise ratio.
Reference Settling
Transient voltage drops across internal reference nodes degrade conversion linearity when high-speed clock cycles outpace capacitor charging recovery times. Switched-capacitor ADCs draw dynamic current spikes from external voltage references during the charge redistribution phase, causing localized droop that manifests as integral nonlinearity. External bypass capacitance placement directly dictates whether settling errors decay below one least significant bit prior to the final comparator decision.
Buffer amplifier bandwidth limitations further constrain the maximum sampling frequency by restricting how fast internal nodes reach precise steady-state potentials.
Parasitic Sensitivity
Substrate coupling and stray capacitance introduce gain errors by shunting a fraction of the transferred charge away from the virtual ground summing node. Switched-capacitor ADCs mitigate parasitic voltage divider effects through bottom-plate sampling techniques that isolate the critical storage node from stray ground paths during the hold phase. Layout symmetry across the integrated circuit die minimizes thermal gradients and gradient-induced capacitance mismatches between adjacent binary-weighted capacitor arrays.
Differential architectures suppress common-mode substrate injection mechanisms while preserving the intended charge ratios required for high-precision analog-to-digital conversion.
