Mitigating Switched Capacitor ADC Load Transient Drift in Integrated References
Mitigating switched-capacitor reference droop requires a low-ESR reservoir capacitor sized to charge-redistribution ratios and Kelvin-connected to analog ground.
Switched Capacitor ADC
Architecture Overview
An electronic analog-to-digital converter architecture utilizes arrays of capacitors and electronic switches to sample and hold analog signals. This switched capacitor ADC translates input voltages into digital codes by redistributing charge across the array. The architecture achieves high linearity and low power consumption without needing high-precision resistors.
It is widely used in high-resolution, low-power applications.
Operating Principle
Two non-overlapping clock phases control the charge transfer between the sampling array and the comparator. In the acquisition phase, the switched capacitor ADC connects the capacitor array to the analog input to acquire the signal. During the conversion phase, the switches alter the connections to execute a binary search algorithm.
This sequential redistribution allows the circuit to determine the corresponding digital code.
Noise Factor
Thermal noise from the switches introduces uncertainty into the sampled voltage, known as kT/C noise. Larger capacitors reduce this thermal noise but increase the drive requirements for the input buffer. Board designers must balance these conflicting requirements to optimize noise performance.
This thermal noise represents the fundamental limit of the converter resolution.
Reference Source
External voltage references must remain extremely stable to maintain accuracy during conversion. Voltage drops on this reference node will directly translate to linearity errors.