Aligning Moving Average Windows with Converters to Eliminate Aliasing Artifacts
Aligning moving average window lengths to match converter sample periods places exact spectral nulls over periodic interference to eliminate aliasing artifacts.
Sample Rate Jitter
Timing Uncertainty
Clock instability in digital-to-analog and analog-to-digital converters introduces noise into the sampling process. This sample rate jitter represents the variation in the timing of the clock pulses that trigger each conversion. It degrades the signal-to-noise ratio of the system, particularly when measuring high-frequency analog signals where the voltage changes rapidly with time.
Phase Noise
Frequency-domain analysis of the clock signal reveals phase noise that is directly related to the timing jitter. When sample rate jitter is present, the clock signal’s energy is spread into sidebands rather than being concentrated at the clock frequency. This spreading mixes with adjacent high-frequency signals, creating unwanted noise in the sampled output.
Mitigation Strategy
Low-noise voltage-controlled crystal oscillators and phase-locked loops are employed to generate a stable clock signal. These clock generators must be powered by clean, dedicated linear regulators to prevent noise on the power rails from modulating the clock phase. This design ensures that the sample rate jitter remains below the level that would degrade the resolution of the converter, maintaining measurement integrity.
Testing Method
Specialized high-speed oscilloscopes and phase noise analyzers are used to measure the jitter of the clock signal. This measurement is performed at the clock pin of the converter to account for any board-level routing noise.