Timing Uncertainty
Temporal variation or noise occurring in the periodic output of a frequency control system used for clock generation. Minimizing phase locked loop jitter is necessary to maintain high data rates in serial communication interfaces and precision timing networks. This jitter appears as a deviation from the ideal position of a clock edge in time.
It is measured in picoseconds or as a phase noise value in the frequency domain.
Signal Noise
Internal components of the loop such as the voltage-controlled oscillator and the phase detector contribute to the total error. High phase locked loop jitter can cause bit errors in digital circuits by reducing the timing margin for data sampling. External noise on the power supply also infiltrates the loop and increases the instability.
Designers use low-noise regulators and careful shielding to isolate the circuit from these influences.
Oscillator Stability
Performance of the system depends on the ability of the loop to track a reference signal while filtering out noise. While a narrow loop bandwidth reduces the impact of reference noise, it can increase the phase locked loop jitter contributed by the internal oscillator. Finding the optimal bandwidth is a critical step in the design of any frequency synthesizer.
This trade-off is verified by analyzing the output spectrum with a signal source analyzer.
Loop Performance
Reliability of the clock signal is confirmed by measuring the jitter over a specific frequency range. Excessive phase locked loop jitter results in a blurred clock signal that can lead to synchronization failure in complex systems. Testing involves observing the clock under various load and temperature conditions.
Stable operation is achieved when the jitter remains below the threshold required by the communication standard.
