Bus Architecture
Two wire serial communication systems establish a shared pathway for low speed digital data transfer between multiple integrated circuits on a local board. The i2c protocol defines controller and target relationships using a serial data line and a serial clock line to coordinate byte oriented transactions. This bus architecture is limited to short physical distances due to high signal attenuation.
Signal Timing
Open drain transmitters require passive pullup components to draw the signal lines to their high logic state when the bus is idle. Clock frequency constraints determine the minimum and maximum rise times allowable under each speed mode. Slow transitions can cause receiving devices to misread addresses or data frames.
Capacitive loading on the lines restricts the max distance of communication.
Address Space
Unique device identifiers are transmitted at the start of every transaction to target specific nodes on the shared bus. Standard seven bit addressing limits the total number of physical nodes, though ten bit extension modes are available for denser configurations.
Pullup Resistance
Selecting correct resistor values balancing power consumption against rise time represents a critical calibration step. Excessive resistance prevents the signal from reaching the high threshold before the next clock pulse, while too little resistance causes high current draw during low states.