Configuring Moving Average Filter Lengths for Decimated Signal Processing
Matching moving average filter length to the decimation factor eliminates alias leakage by placing transfer function zeros directly on downsampling fold points.
Hogenauer Structure
Filter Architecture
Digital hardware design uses a cascaded integrator-comb filter implementation to execute decimation or interpolation without utilizing multipliers. This hogenauer structure utilizes a series of integrators operating at the high sampling rate followed by a series of combs operating at the low sampling rate. The lack of multipliers reduces both the silicon area and power consumption of digital circuits.
Register Growth
Intermediate arithmetic stages require specific bit-width expansion to prevent loss of precision or overflow errors. Because the gain of each filter stage is non-unity, registers must grow in size from the input to the output. The Hogenauer methodology calculates the exact register width required at each stage to avoid truncation noise.
Decimation Factor
Digital decimators use the change in sample rates to process signals from high-speed delta-sigma analog-to-digital converters. Adjusting the decimation factor modifies the frequency response of the filter and shifts the position of the spectral nulls. The design achieves filtering through addition and subtraction operations, avoiding the complex coefficients of standard finite impulse response designs.
This simplicity allows the filter to handle extremely high data rates in field-programmable gate arrays. High throughput is maintained because the high-speed section contains only simple accumulators. The comb section then executes at the reduced sampling rate, which minimizes the overall dynamic power consumption of the device.
Resource Efficiency
Metrological devices optimize their silicon footprints by discarding unused lower bits in the early filter stages. This systematic truncation maintains a specified signal-to-noise ratio while reducing the required logic gates. Software simulations verify the truncation limits against the theoretical limits of the Hogenauer structure before hardware implementation.