Signal Component
Digital filter structure that enables the continuous adjustment of timing offsets by using a polynomial representation of the interpolation kernel. Implementing a farrow fractional delay allows for sub-sample precision in systems where the sampling clock is not synchronized with the incoming data. It functions by computing a set of fixed filter coefficients and multiplying them by the desired delay value.
This specific topology separates the delay parameter from the filter weights, making it suitable for real-time tracking.
Mathematical Operation
Polynomial evaluation occurs at every sample interval to produce the interpolated output. A third-order or fourth-order approximation is common in high-fidelity applications to minimize aliasing. Calculation efficiency remains high because the core structure uses a fixed set of multipliers and delays.
Hardware Constraint
Quantization of the delay parameter introduces a noise floor that limits the dynamic range of the system. Phase linearity depends on the symmetry of the underlying impulse response and the order of the polynomial. Designers choose the order based on a tradeoff between processing power and stopband attenuation.
Clock Integration
Resampling tasks in software-defined radio rely on this method to bridge different data rates. Because the delay is a variable input, the filter adapts to drift in the master oscillator without requiring a full recalculation of the coefficients. Error accumulation is avoided through periodic recalibration against a reference pulse.