Characterizing Dynamic Front End Filter Group Delay Mismatches across Dual Sourced Commercial Sensors
Unstated front-end filter group delay mismatches across dual-sourced sensors create dynamic phase errors that destabilize real-time fusion loops.
Sinc Decimation Filter
Digital Filtering
Discrete signal processing logic averages a high-frequency stream of data points to derive lower-frequency samples. A sinc decimation filter executes this operation by convolving an incoming bitstream with a rectangular window function, effectively acting as a low-pass operator. This calculation removes high-frequency noise and prevents aliasing by forcing the bandwidth to fit the output sample rate.
Mathematical Foundation
Summation occurs over a predetermined number of input cycles known as the decimation ratio. Each output represents the moving average of these inputs, which creates null points in the frequency response that correspond to the sampling frequency. Adjusting the length of this window defines the trade-off between the depth of the attenuation and the passband width.
Implementation Logic
Hardware counters perform the addition of incoming pulses before the system divides the result to complete the averaging process. This architecture replaces complex multiplication with simple addition to maintain high processing speeds on embedded platforms. Integrated circuits use this method because it avoids the hardware overhead associated with traditional multi-tap finite impulse response structures.
Performance Constraint
Quantization noise from the modulator stage limits the effective resolution of the converted signal. Errors in the timing of the input pulses introduce jitter that manifests as an increased noise floor in the filtered output. Calibrated systems must match the decimation ratio to the stability of the input clock to ensure the integrity of the data remains within the target error margin.