Power Budget per Reading across Competing Sensing Principles
Sensing power budgets depend on physical excitation energy, analog settling delays, and converter sampling overhead across operating duty cycles.
SAR Converter Power
Conversion Efficiency
Successive approximation register analog to digital converters determine a digital value by testing bits in sequence. The sar converter power profile is dominated by the charging and discharging of the internal capacitor DAC array during each bit trial. Because the circuitry only draws significant current while switching, the total consumption scales linearly with the sample rate.
Static Consumption
Between conversions, the device enters a low power state where only the reference buffer and the internal clock remain active. Minimizing sar converter power involves keeping the ADC in sleep mode for as long as possible. High speed applications require more energy because the charging cycles happen more frequently.
Reference Drive
The voltage reference must provide enough current to charge the input capacitors within the acquisition time without sagging. If the sar converter power management is poor, the reference voltage will fluctuate and cause bit errors in the conversion. External bypass capacitors are used to provide the necessary charge locally.
Proper PCB layout reduces the resistance of the power path and improves the overall efficiency.
Dynamic Scaling
Modern designs allow for the adjustment of the resolution to save energy. Lowering the number of bits reduces the sar converter power because fewer comparison steps are required.