Print Aperture and PCB Stackup Tradeoffs in High Density Packages
Fine-pitch package assembly requires pairing stencil foil reductions with thin outer-layer dielectrics to maintain solder transfer and controlled impedance.
Registration Tolerance
Alignment Margin
Positional deviation limits define the acceptable misalignment between different layers of a multi-layer circuit board. This limit, known as registration tolerance, ensures that drilled vias connect accurately with the internal copper pads of the stackup. It is verified during manufacturing using specialized optical alignment marks.
Connection Reliability
Poor layer alignment causes drilled holes to breakout of the copper pads, destroying the electrical connection. Maintaining a tight registration tolerance ensures that the annular ring of copper remaining around each hole is sufficient to withstand thermal stress. This margin prevents failure of the internal connections during the assembly process.
Measurement Method
Automated inspection tools measure the offset of target patterns on each layer relative to a master coordinate system. If the measured offset exceeds the designated registration tolerance, the panel is rejected before drill and etch processes proceed. This inspection step minimizes scrap rates by catching errors early in the production run.
Mechanical Drift
Thermal expansion of the carrier material during lamination can cause layers to shift relative to each other. This physical expansion degrades the registration tolerance across large panels, requiring careful control of lamination press temperatures. Manufacturers adjust their scaling factors to compensate for this expected shrinkage and expansion, ensuring that the final multi-layer boards meet the required standards of alignment and connectivity.