Temporal Constraint
The longest allowable interval for which a clock signal or a data pulse is extended beyond its nominal period defines the limits of synchronous communication. This maximum stretch duration is a parameter in protocols where the peripheral device controls the bus speed to match its processing rate.
Bus Stability
Excessive delays in signal transitions can cause the master controller to timeout and abort the current transaction to prevent a total bus hang. Exceeding the maximum stretch duration often triggers an error flag in the communication stack of the host processor.
Measurement Methodology
Oscilloscope measurements verify the interval between the initial edge and the trailing edge of the stretched pulse under various capacitive loading conditions. The maximum stretch duration is usually specified at the worst case operating temperature where internal oscillator drift is highest.
Hardware Interaction
Pull up resistor values influence the rise time and impact the effective length of the signal extension. Determining the maximum stretch duration involves a trade off between system throughput and the processing capabilities of the slowest node on the network. A weak pull up resistor increases the time needed for the signal to reach the logic high threshold, which consumes a portion of the timing budget allocated for the stretch.
Timing constraints ensure the controller maintains synchronization with the peripheral during extended clock cycles.
